Solid-state memory is used widely to store information. So-called “flash” memory is a particular type of solid-state memory that is also commonly referred to as non-volatile RAM (NVRAM). NVRAM requires no power for storage of information. NVRAM can be found in a variety of consumer devices, control systems and servers (e.g., blades of a data center).
Solid-state memory has a limited lifetime. Often, the lifetime is specified in terms of write-erase cycles (e.g., several million cycles or more) and depends on quality of manufacture, etc. As a block approaches its lifetime number of write-erase cycles, the reliability of that block becomes suspect. Depending on the nature of the data stored, a solid-state memory may last days or years.
With respect to write and erase operations, a write operation typically writes data (“0” s) to pages that may be a couple of kilobytes in size while an erase operation typically erases data (“1” s) from a number of pages, which are often referred to as blocks. With respect to read operations, a read operation can occur quickly, usually in microseconds, and does not count as a cycle operation.
Solid-state memory may support a log file system. A log file system requires storage of a log. The log tracks addresses or locations for data stored in solid-state memory. Depending on how the log file is stored and updated, it may increase life of solid-state memory or it may decrease life of solid-state memory. For example, if it is stored in a dedicated location, the memory may fail once that location reaches its write-erase cycle limit. Such issues exist for a so-called “inode” of a log file system when it lives at a dedicated memory location.
Wear-levelling is a term generally applied to techniques that aim to “level” wear of solid-state memory in a manner that extends lifetime. Conventional approaches to wear-levelling include use of chip firmware or file system drivers to count writes and dynamically remap blocks to spread the write operations. Another approach is to perform write verification and remapping to spare sectors in case of write failure, a technique called bad block management (BBM). For portable consumer devices, such techniques may extend the life of flash memory beyond the life of its portable consumer device. Such devices can often accept some degree of data loss. For high reliability data storage, however, it is not advisable to use flash memory that has been through a large number of programming cycles. This limitation does not apply to read-only applications such as thin clients and routers, which are only programmed once or at most a few times during their lifetime.
As to specific terminology often associated with NVRAM, an address is a row address and a column address where the row address identifies the page and block to be accessed and where the column address identifies the byte or word within a page to access. A block, as mentioned, consists of multiple pages and is typically the smallest addressable unit for erase operations. A logical unit number (LUN) is typically the minimum unit that can independently execute commands and report status. A page is typically the smallest addressable unit for read and program operations. For targets that support partial page programming, the smallest addressable unit for program operations is a partial page if there are partial programming constraints. A page register is normally used to read data that was transferred from a NVRAM array. For program operations, the data is placed in this register prior to transferring the data to the array.
Often, each LUN has at least one page register, which is used for temporary storage of data before it is moved to a page within a NVRAM array or after it is moved from a page within the array. In an example, if the number of pages per block is 96, then the page address is normally rounded to 7 bits such that it can address pages in the range of 0 to 127. In this case, the host will not access pages in the range from 96 to 127 as these pages are not supported. The page address always uses the least significant row address bits. The block address uses the middle row address bits and the LUN address uses the most significant row address bit(s).
Various exemplary techniques are described herein for optimizing usage of solid-state memory. Particular techniques perform wear-levelling to extend lifetime of solid-state memory, especially NVRAM.